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serialflash tm memory with block lock tm protection 64k/32k/16k 8k/4k/2k x 8 bit xicor, 1995, 1996 patents pending 6686-3.8 8/29/96 t3/c0/d0 sh 1 characteristics subject to change without notice X24F064/032/016 functional diagram features 1.8v to 3.6v or 5v ?nivolt read and program power supply versions low power cmos active read current less than 1ma active program current less than 3ma standby current less than 1 m a internally organized 8k/4k/2k x 8 new programmable block lock protection software write protection programmable hardware write protect block lock (0, 1/4, 1/2, or all of the flash memory array) 2 wire serial interface bidirectional data transfer protocol 32 byte sector programming self timed program cycle typical programming time of 5ms per sector high reliability endurance: 100,000 cycles per byte data retention: 100 years available packages 8-lead pdip 8-lead soic (jedec) 14-lead tssop (x24f032/016) 20-lead tssop (X24F064) description the X24F064/032/016 is a cmos serialflash memory family, internally organized 8k/4k/2k x 8. the family features a serial interface and software protocol allowing operation on a simple two wire bus. device select inputs (s 0 , s 1 , s 2 ) allow up to eight devices to share a common two wire bus. a program protect register accessed at the highest address location, provides three new programming protection features: software programming protection, block lock protection, and hardware programming protection. the software programming protection feature prevents any nonvolatile writes to the device until the wel bit in the program protect register is set. the block lock tm protection feature allows the user to individually protect four blocks of the array by program- ming two bits in the programming protect register. the programmable hardware program protect feature allows the user to install each device with pp tied to v cc , program the entire memory array in place, and then enable the hardware programming protection by programming a ppen bit in the program protect register. after this, selected blocks of the array, including the program protect register itself, are permanently protected from being programmed. 6686 ill f01.5 command decode and control logic x decode logic sectored memory array sda scl s 2 /s 2 program protect register programming control logic pp high voltage control sector decode logic 32 8 data register s 1 /s 1 s 0 /s 0 serialflash ? memory and block lock ? protection are trademarks of xicor, inc. a pplication n ote a v a i l a b l e an76 ?an78 ?an81 ?an87
X24F064/032/016 2 xicor serialflash memories are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull- up resistor selection graph at the end of this data sheet. device select (s 0 , s 0 , s 1 , s 1 , s 2 , s 2 ) the device select inputs are used to set the device select bits of the 8-bit slave address. this allows multiple devices to share a common bus. these inputs can be static or actively driven. if used statically they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven with cmos levels (driven to v cc or v ss ). program protect (pp) the program protect input controls the hardware program protect feature. when held low, hardware program protection is disabled and the X24F064/ 032/016 can be programmed normally. when this input is held high, and the ppen bit in the program protect register is set high, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the program protect register itself. pin names 6686 frm t01.1 symbol description s 0 , s 0 , s 1 , s 1 , s 2 , s 2 device select inputs sda serial data scl serial clock pp program protect v ss ground v cc supply voltage nc no connect pin configuration s 0 s 1 nc nc nc s 2 v ss 14-lead tssop v cc pp nc nc nc scl sda 14-lead tssop s 0 s 1 nc nc nc s 2 v ss v cc pp nc nc nc scl sda 20-lead tssop nc nc s 1 nc nc nc s 2 v ss nc nc nc v cc pp nc nc nc scl sda nc nc v cc pp scl sda s 0 s 1 s 2 v ss 1 2 3 4 8 7 6 5 8-lead dip & soic 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v cc pp scl sda s 0 s 1 s 2 v ss 1 2 3 4 8 7 6 5 8-lead dip & soic 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v cc pp scl sda nc s 1 s 2 v ss 1 2 3 4 8 7 6 5 8-lead dip & soic 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 X24F064 x24f032 x24f016 6686 ill f02.4
X24F064/032/016 3 device operation the X24F064/032/016 supports a bidirectional bus ori- ented protocol. the protocol defines any device that sends data onto the bus as a transmitter, and the re- ceiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data trans- fers, and provide the clock for both transmit and receive operations. therefore, the X24F064/032/016 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the X24F064/032/016 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. scl sda data stable data change 6686 ill f04 scl sda start bit stop bit 6686 ill f05 figure 1. data validity figure 2. definition of start and stop notes: (5) typical values are for t a = 25 c and nominal supply voltage (2.7v) (6) t pr is the minimum cycle time from the system perspective when polling techniques are not used. it is the maximum time the device requires to perform the internal program operation.
X24F064/032/016 4 stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the X24F064/032/016 will respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the X24F064/032/016 will respond with an acknowledge after the receipt of each subsequent eight-bit word. in the read mode the X24F064/032/016 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the X24F064/032/016 will continue to transmit data. if an acknowledge is not detected, the device will terminate further data transmissions. the master must then issue a stop condition to return the X24F064/032/016 to the standby power mode and place the device into a known state. figure 3. acknowledge response from receiver 6686 ill f06 scl from master data output from transmitter 1 89 data output from receiver start acknowledge
X24F064/032/016 5 device addressing following a start condition the master must output the address of the slave it is accessing (see figure 4). the next two bits are the device select bits. a system could have up to eight x24f032/016s on the bus or up to four 24f064s on the bus. the device addresses are de?ed by the state of the s 0 , s 1 , and s 2 inputs. note some of the slave addresses must be the inverse of the corresponding input pin. figure 4. slave address 6686 ill f07.4 s2 a9 a8 r/w device select s1 a12 high order sector address a11 a10 X24F064 s2 a9 a8 r/w device select s1 s0 high order sector address a11 a10 x24f032 1 a9 a8 r/w device type identifier s2 s1 high order sector address s0 a10 x24f016 device select also included in the slave address is an extension of the arrays address which is concatenated with the eight bits of address in the sector address ?ld, providing direct access to the entire serialflash memory array. the last bit of the slave address de?es the operation to be performed. when set high a read operation is selected, when set low a program operation is selected. following the start condition, the X24F064/032/016 monitors the sda bus comparing the slave address being transmitted with its slave address device type identi?r. upon a correct comparison of the device select inputs, the X24F064/032/016 outputs an acknowledge on the sda line. depending on the state of the r/w bit, the X24F064/032/016 will execute a read or program operation. programming operations the X24F064/032/016 offers a 32-byte sector pro- gramming operation. for a program operation, the X24F064/032/016 requires a second address field. this field contains the address of the first byte in the sector. upon receipt of the address, comprised of eight bits, the X24F064/032/016 responds with an ac- knowledge and awaits the next eight bits of data, again responding with an acknowledge. the master then transmits 31 more bytes. after the receipt of each byte, the X24F064/032/016 will respond with an acknowledge. figure 5. sector programming bus activity: master sda line bus activity: x24f016/032/064 s t a r t slave address s s t o p p a c k a c k a c k a c k a c k sector address data n data n+1 data n+31 6686 ill f10.3
X24F064/032/016 6 flow 1. ack polling sequence after the receipt of each byte, the five low order ad- dress bits are internally incremented by one. the high order bits of the sector address remain constant. if the master should transmit more or less than 32 bytes prior to generating the stop condition, the contents of the sector cannot be guaranteed. all inputs are disabled until completion of the internal program cycle. refer to figure 5 for the address, acknowledge and data trans- fer sequence. acknowledge polling the max write cycle time can be significantly reduced using acknowledge polling. to initiate acknowledge polling, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle, then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to flow 1. read operations read operations are initiated in the same manner as program operations with the exception that the r/w bit of the slave address is set high. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a ?on? care.?to terminate a read op- eration, the master must either issue a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. 6686 ill f09.1 program operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue sector address proceed issue stop no yes yes proceed issue stop no
X24F064/032/016 7 current address read internally, the X24F064/032/016 contains an ad- dress counter that maintains the address of the last byte read, incremented by one byte. therefore, if the last read was from address n, the next read opera- tion accesses data from address n + 1. upon receipt of the slave address with the r/w set high, the X24F064/032/016 issues an acknowledge and trans- mits the eight-bit word. the read operation is termi- nated by the master; by not responding with an acknowledge and by issuing a stop condition. refer to figure 6 for the sequence of address, acknowl- edge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to is- suing the slave address with the r/w bit set high, the master must first perform a ?ummy?write operation. the master issues the start condition, and the slave ad- dress with the r/w bit set low, followed by the byte address it is to read. after the byte address acknowl- edge, the master immediately reissues the start condi- tion and the slave address with the r/w bit set high. this will be followed by an acknowledge from the X24F064/032/016 and then by the eight-bit byte. the read operation is terminated by the master; by not re- sponding with an acknowledge and by issuing a stop condition. refer to figure 7 for the address, acknowl- edge and data transfer sequence. figure 7. random read bus activity: master sda line bus activity: x24f016/032/064 s t a r t slave address s a c k 6686 ill f12.3 s t a r t s byte address n a c k slave address data n a c k s t o p p figure 6. current address read bus activity: master sda line bus activity: x24f016/032/064 s t a r t slave address s s t o p p a c k data 6686 ill f11.1
X24F064/032/016 8 sequential read sequential reads can be initiated as either a current address read or random access read. the first byte is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. the X24F064/032/016 continues to output data for each acknowledge received. the read operation is terminated by the master; by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space, the counter ?olls over?to 0 and the X24F064/032/016 continues to output data for each acknowledge received. refer to figure 8 for the address, acknowledge and data transfer sequence. figure 8. sequential read bus activity: master sda line bus activity: x24f016/032/064 slave address a c k 6686 ill f13.1 a c k data n+x s t o p p data n a c k data n+1 a c k data n+2 figure 9. typical system configuration master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver pull-up resistors sda scl v cc 6686 ill f14
X24F064/032/016 9 program protect register the program protect register (ppr) is accessed at the highest address of each device: X24F064 = 1fff x24f032 = 0fff x24f016 = 07ff figure 10. program protect register ppr.1 = wel write enable latch (volatile) 0 = write enable latch reset, programming disabled 1 = write enable latch set, programming enabled if wel = 0 then ?o ack after ?st byte of input data. ppr.2 = rwel register write enable latch (volatile) 0 = register write enable latch reset, programming disabled 1 = register write enable latch set, programming enabled ppr.3, ppr.4 = bl0, bl1 block lock bits (nonvolatile) (see block lock bits section for definition) ppr.7 = ppen programming protect enable bit (nonvolatile) (see programmable hardware program protect sec- tion for definition) writing to the program protect register the program protect register is written by performing a write of one byte directly to the highest address loca- tion. during normal sector programming, the byte in the array at the highest address will be written instead of the program protect register (assuming program- ming is not disabled by the block lock register). the state of the program protect register can be read by performing a random read at the highest address location at any time. if a sequential read starting at any 76543 2 1 0 ppen 0 0 bl1 bl0 rwel wel 0 6686 ill f15 other address than the highest address location is performed, the contents of the byte in the array at the highest address location is read out instead of the program protect register. wel and rwel are volatile latches that power-up in the low (disabled) state. a write to any address other than the highest address location, where the program protect register is located, will be ignored (no ack) until the wel bit is set high. the wel bit is set by writing 0000001x to the highest address location. once set, wel remains high until either reset (by writing 00000000 to the highest address location) or until the part powers-up again. the rwel bit controls writes to the block lock bits. rwel is set by ?st setting wel = 1 and then writing 0000011x to the highest address location. rwel must be set in order to change the block lock bits (bl0 and bl1) or the ppen bit. rwel is reset when the block lock or ppen bits are changed, or when the part powers-up again. programming the bl or ppen bits a three step sequence is required to change the nonvolatile block lock or program protect enable: 1) set wel = 1 (write 00000010 to the highest address location, volatile write cycle) (start) 2) set rwel = 1 (write 00000110 to the highest address location, volatile write cycle) (start) 3) set bl1, bl0, and/or ppen bits (write w00yz010 to the highest address location) w = ppen, y = bl1, z = bl0, (stop) step 3 is a nonvolatile program cycle, requiring 10ms to complete. rwel is reset (0) by this program cycle, requiring another program cycle to set rwel again before the block lock bits can be changed. rwel must be 0 in step 3; if w00yz110 is written to the highest address location, rwel is set but ppen, bl1 and bl0 are not changed (the device remains at step 2).
X24F064/032/016 10 block lock bits the block lock bits bl0 and bl1 determine which blocks of the memory are write-protected: table 1. block lock bits 6686 frm t02 bl1 bl0 array locked 0 0 none 0 1 upper 1/4 1 0 upper 1/2 1 1 full array (wpr not included) programmable hardware program protect the program protect (pp) pin and the program protect enable (ppen) bit in the program protect register control the programmable hardware program protect feature. hardware program protection is enabled when the pp pin and the ppen bit are both high , and disabled when either the pp pin is low or the ppen bit is low. when the chip is hardware program- protected, nonvolatile programming is disabled, including the program protect register, the bl bits and the ppen bit itself, as well as to block locked sections in the memory array. only the sections of the memory array that are not block locked can be written. note that since the ppen bit is program-protected, it cannot be changed back to a low state, and program protec- tion is disabled as long as the pp pin is held high. table 2 de?es the program protection status for each state of ppen and pp. table 2. program protect status table 6686 frm t03 pp ppen memory array (not block locked) memory array (block locked) bl bits ppen bit 0 x programmable locked programmable programmable x 0 programmable locked programmable programmable 1 1 programmable locked locked locked
X24F064/032/016 11 absolute maximum ratings* temperature under bias X24F064/032/016 ...................... ?5 c to +135 c storage temperature........................ ?5 c to +150 c voltage on any pin with respect to v ss .................................... ?v to +7v d.c. output current..............................................5ma lead temperature (soldering, 10 seconds)...... 300 c *comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) 6686 frm t06.4 capacitance t a = +25 c, f = 1mhz, v cc = 2.7v 6686 frm t07 notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not 100% tested. (3) this parameter is periodically sampled and not 100% tested. limits symbol parameter min. max. units test conditions i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100khz, sda = open, all other inputs = v ss or v cc ?0.3v i cc2 v cc supply current (write) 3 ma i sb1 (1) v cc standby current 1 m a scl = sda = v cc , all other inputs = v ss or v cc ?0.3v, v cc = 3.6v i sb2 (1) v cc standby current 10 m a scl = sda = v cc , all other inputs = v ss or v cc ?0.3v, v cc = 5v 10% i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v ll (2) input low voltage ? v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 1 , s 2 , scl) 6pf v in = 0v recommended operating conditions 6686 frm t04.2 temperature min. max. commercial 0 c +70 c extended ?0 c +85 c industrial ?0 c +85 c 6686 frm t05.2 supply voltage limits X24F064/032/016 1.8v to 3.6v X24F064/032/016? 4.5v to 5.5v
X24F064/032/016 12 a.c. conditions of test 6686 frm t08 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 equivalent a.c. load circuit 6686 ill f16.1 5v 1533 w 100pf output 2.7v 1533 w 100pf output a.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) read & write cycle limits 6686 frm t09.1 power-up timing (4) 6686 frm t10 notes: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4 m s t low clock low period 4.7 m s t high clock high period 4 m s t su:sta start condition setup time (for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 m s t dh data out hold time 300 ns symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms
X24F064/032/016 13 symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance the program cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the program cycle, the X24F064/032/016 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing 6686 ill f17 t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high program cycle limits 6686 frm t11.1 symbol parameter min. typ. (5) max. units t pr (6) program cycle time 5 10 ms bus timing 6686 ill f18 scl sda 8th bit word n ack t wr stop condition start condition notes: (5) typical values are for t a = 25 c and nominal supply voltage (2.7v). (6) t wr is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal program operation. guidelines for calculating typical values of bus pull-up resistors 6686 ill f19.1 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k w ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.2k w
X24F064/032/016 14 packaging information 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
X24F064/032/016 15 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 3926 fhd f22.1 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
X24F064/032/016 16 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 fhd f32
X24F064/032/016 17 packaging information note: all dimensions in inches (in parentheses in millimeters) 20-lead plastic, tssop package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .300 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 fhd f45
X24F064/032/016 18 ordering information part mark convention device x24fxxx x x temperature range blank = commercial = 0 c to +70 c e = extended = ?0 c to +85 c package p = 8-lead plastic dip p = 8-lead plastic dip blank = 8-lead soic (jedec) blank = 1.8v to 3.6v, 0 c to +70 c e = 1.8v to 3.6v, ?0 c to +85 c x24fxxx x x limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. s = 8-lead soic (jedec) v = 14-lead tssop x24f032 x24f016 X24F064 v = 14/20-lead tssop X24F064 x24f032 x24f016 X24F064 x24f032 x24f016 v cc range blank = 1.8v to 3.6v 5 = 4.5v to 5.5v ? p = 8-lead plastic dip s = 8-lead soic (jedec) v = 20-lead tssop 5 = 4.5v to 5.5v, 0 c to +70 c i5 = 4.5v to 5.5v, ?0 c to +85 c i = industrial = ?0 c to +85 c
X24F064/032/016 19 notes
X24F064/032/016 20 u.s. sales offices corporate of?e xicor inc. 1511 bu ckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne@smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se@smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma@smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 708/372-3200 fax: 708/372-3210 e-mail: xicor-nc@smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 214/669-2022 fax: 214/644-5835 e-mail: xicor-sc@smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw@smtpgate.xicor.com northwest region xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw@smtpgate.xicor.com international sales offices europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.700544 fax: (44) 1933.700533 e-mail: xicor-uk@smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm@smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp@smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw@smtpgate.xicor.com singapore/malaysia/india xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw@smtpgate.xicor.com korea xicor korea 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2551.2750 fax: (82) 2551.2710 e-mail: xicor-ka@smtpgate.xicor.com ( ) = country code xicor, inc., marketing dept. 1511 buc keye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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